The present invention relates to a CRC operation unit and a CRC operation method for generating a cyclic redundancy check (CRC) code that is an error detection code for detection of an error occurring in transmitting/receiving data when the transmitting/receiving data is transmitted via a communication path or when the data is processed for transmission, or detecting a code error in transmitting/receiving data to which such an error detection code has been added.
CRC is an error-detecting system frequently used in digital communication, which detects an error in the following manner. On the transmitter side, transmitting data, which is considered as a high-order polynomial, is divided by a predetermined generating polynomial. The resultant remainder is added to the end of the transmitting data as a CRC code (encoding). On the receiver side, the transmitted data is divided by the same generating polynomial (decoding). If the remainder is zero, the transmitted data is determined as having no error. If the remainder is not zero, the transmitted data is determined as having an error (error detection). As the generating polynomial, the following are used in actual CRC, for example.
(1) CRC-12
(2) CRC-16
(3) CRC-CCITT
The encoding and error detection as described above, which are hereinafter called CRC operation, may be implemented by a CRC operation unit that executes CRC operation by hardware. The CRC operation unit uses a divider constructed of a combination of a shift register and an exclusive OR gate. In this type of unit, the generating polynomial is determined by how the shift register is connected with the exclusive OR gate. Therefore, this type of unit is not allowed to change the generating polynomial within one unit. That is, a different unit is required if a different generating polynomial is used. Moreover, it is necessary to provide units capable of using the same generating polynomial on the transmitter and receiver sides.
A unit that executes CRC operation by software is known as a CRC operation unit capable of flexibly using various generating polynomials. This type of unit can easily use various generating polynomials by only changing a program or data. This type of unit however has the following problems. CRC operation, which is normally executed by a processor in a communication terminal, tends to put a great load on the processor, resulting in lowering the processing capability of the communication terminal. Moreover, CRC operation by software is low in operation speed and thus is not suitable for high-speed communication.
Units capable of realizing both flexible use of generating polynomials and high-speed CRC operation have been disclosed. For example, Japanese Laid-Open Patent Publication No. 5-151007 discloses a unit constructed of a combination of a generating polynomial setting register, a shift register, and an exclusive OR gate. This unit performs CRC operation by hardware and thus enables high-speed processing. In addition, the unit can use various generating polynomials by changing the generating polynomial set in the generating polynomial setting register.
The CRC operation unit as described above uses exclusive circuits specialized for CRC operation. This disadvantageously increases the circuit scale of a communication unit and the like. In addition, while it is possible to use various generating polynomials having the same bit length as that of the generating polynomial setting register, no consideration is made for use of generating polynomials having different bit lengths.
An object of the present invention is providing a CRC operation unit capable of performing high-speed CRC operation and flexibly using various generating polynomials without causing significant increase in circuit scale.
The CRC operation unit of the present invention includes: generating polynomial supply means for holding data representing a generating polynomial and selectively outputting the data representing a generating polynomial or zero data of which all bits have a value of 0; operation data supply means for outputting operation data to be subjected to CRC operation; and arithmetic and logic operation means for performing exclusive OR operation between the data representing a generating polynomial or the zero data and the operation data, wherein the generating polynomial supply means selects the data representing a generating polynomial or the zero data depending on a value of the MSB of operation results from the arithmetic and logic operation means, and the operation data supply means outputs, as the operation data, data composed of: values of bits in lower order than the MSB of the operation results from the arithmetic and logic operation means as values of higher-order bits of the operation data; and a value of the MSB of unprocessed data to be subjected to CRC operation as a value of the LSB of the operation data.
The generating polynomial supply means may include: a first register for holding the data representing a generating polynomial; and a selector for selectively outputting the data representing a generating polynomial or the zero data, for example, and the operation data supply means may include: a second register for holding the operation results from the arithmetic and logic operation means; a shifter for shifting the operation results held in the second register leftward by one bit and outputting results; a memory for holding the unprocessed data to be subjected to CRC operation; and a shift register for holding part of the unprocessed data to be subjected to CRC operation transferred from the memory, outputting a value of the MSB of the held data, and shifting bits of the held data leftward one by one, for example.
With the above construction, the CRC operation unit can easily use various generating polynomials flexibly by changing the data representing a generating polynomial to be held in the generating polynomial supply means. In addition, the selection of the data representing a generating polynomial or the zero data to be input to the arithmetic and logic operation means and the generation of the operation data to be subjected to CRC operation are performed automatically, not by executing a program instruction. This realizes high-speed CRC operation. Moreover, since components provided for normal processors can be primarily used for the generating polynomial supply means, the operation data supply means, and the arithmetic and logic operation means, it is possible to minimize the circuit scale of the entire apparatus including the CRC operation unit.
The CRC operation unit may further include operation instruction execution control means, wherein the operation instruction execution control means controls, under a predetermined operation instruction, output of the data representing a generating polynomial or the zero data by the generating polynomial supply means, output of the operation data by the operation data supply means, and execution of the exclusive OR operation by the arithmetic and logic operation means.
The operation instruction execution control means may control, under a predetermined operation instruction, operations of the generating polynomial supply means, the operation data supply means, and the arithmetic and logic operation means for one-time execution of the exclusive OR operation by the arithmetic and logic operation means.
Alternatively, the operation instruction execution control means may control, under a predetermined operation instruction, operations of the generating polynomial supply means, the operation data supply means, and the arithmetic and logic operation means for execution of the exclusive OR operation for all the unprocessed data to be subjected to CRC operation by the arithmetic and logic operation means.
Otherwise, the operation instruction execution control means may control, under a predetermined operation instruction, operations of the generating polynomial supply means, the operation data supply means, and the arithmetic and logic operation means for execution of the exclusive OR operation for values of all bits held in the shift register by the arithmetic and logic operation means.
With above constructions, it is possible to enhance the flexibility of the CRC processing by increasing the degree of freedom in the combination of operation instructions or enhance the speed of the CRC processing with a small number of operation instructions.
After completion of the exclusive OR operation for all of the unprocessed data to be subjected to CRC operation by the arithmetic and logic operation means, the values held in the second register may be stored in the memory.
Alternatively, after completion of the exclusive OR operation for all of the unprocessed data to be subjected to CRC operation by the arithmetic and logic operation means, whether or not the unprocessed data to be subjected to CRC operation has an error may be determined by examining whether or not the values held in the second register are 0.
The above constructions facilitate CRC encoding and data error detection.
When the number of bits of the data representing a generating polynomial is smaller than the number of bits allowed to be held by the generating polynomial supply means, the generating polynomial supply means may left-justify the data representing a generating polynomial and give 0 to the remaining lower-order bit(s).
The above construction enhances the flexibility of use of various generating polynomials in the number of bits, in addition to the type.
The CRC operation unit of another embodiment of the present invention includes: generating polynomial holding means for holding data representing a generating polynomial; and CRC operation means for performing CRC operation based on the data representing a generating polynomial and data to be subjected to CRC operation, wherein, when the number of bits of the data representing a generating polynomial is smaller than the number of bits allowed to be held by the generating polynomial holding means, the generating polynomial holding means left-justifies the data representing a generating polynomial and gives 0 to the remaining lower-order bit(s).
The above construction enhances the flexibility of use of various generating polynomials in the number of bits, in addition to the type, even in the case of using exclusive circuits specialized for CRC operation.